Shi-Yu Huang,Kwang-Ting (Tim) Cheng's Formal Equivalence Checking and Design Debugging (Frontiers PDF

By Shi-Yu Huang,Kwang-Ting (Tim) Cheng

Formal Equivalence Checking and layout Debugging covers significant themes in layout verification: good judgment equivalence checking and layout debugging. the 1st a part of the publication reports the layout difficulties that require good judgment equivalence checking and describes the underlying applied sciences which are used to unravel them. a few novel ways to the issues of verifying layout revisions after in depth sequential changes corresponding to retiming are defined in element.
the second one a part of the booklet provides a radical survey of past and fresh literature on layout mistakes analysis and layout blunders correction. This half additionally offers an in-depth research of the algorithms utilized in common sense debugging software program courses, ErrorTracer and AutoFix, constructed by way of the authors.
From the Foreword:
`With the adoption of the static sign-off method of verifying circuit implementations the application-specific built-in circuit (ASIC) will event the 1st radical methodological revolution because the adoption of good judgment synthesis. Equivalence checking is among the severe components of this methodological revolution. This e-book is well timed for both the dressmaker trying to larger comprehend the mechanics of equivalence checking or for the CAD researcher who needs to enquire well-motivated study difficulties resembling equivalence checking of retimed designs or errors analysis in sequential circuits.'
Kurt Keutzer, collage of California, Berkeley

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Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing) by Shi-Yu Huang,Kwang-Ting (Tim) Cheng


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